CSCARBL=0, CSCAFBH=0, CSCBFAH=0, CSELCB=0, CCLR=0, CSCBRAL=0, CSELCD=0, CSCBRAH=0, CSGTRGAF=0, CSELCA=0, CSGTRGAR=0, CSCBFAL=0, CSCAFBL=0, CSCARBH=0, CSELCC=0, CSGTRGBF=0, CSGTRGBR=0
General PWM Timer Clear Source Select Register
| CSGTRGAR | GTETRGA Pin Rising Input Source Counter Clear Enable 0 (0): Counter clear disabled on the rising edge of GTETRGA input 1 (1): Counter clear enabled on the rising edge of GTETRGA input |
| CSGTRGAF | GTETRGA Pin Falling Input Source Counter Clear Enable 0 (0): Counter clear disabled on the falling edge of GTETRGA input 1 (1): Counter clear enabled on the falling edge of GTETRGA input |
| CSGTRGBR | GTETRGB Pin Rising Input Source Counter Clear Enable 0 (0): Disable counter clear on the rising edge of GTETRGB input 1 (1): Enable counter clear on the rising edge of GTETRGB input |
| CSGTRGBF | GTETRGB Pin Falling Input Source Counter Clear Enable 0 (0): Counter clear disabled on the falling edge of GTETRGB input 1 (1): Counter clear enabled on the falling edge of GTETRGB input |
| CSCARBL | GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Clear Enable 0 (0): Counter clear disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 1 (1): Counter clear enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 |
| CSCARBH | GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Clear Enable 0 (0): Counter clear disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 1 (1): Counter clear enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 |
| CSCAFBL | GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Clear Enable 0 (0): Counter clear disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 1 (1): Counter clear enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 |
| CSCAFBH | GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Clear Enable 0 (0): Counter clear disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 1 (1): Counter clear enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 |
| CSCBRAL | GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Clear Enable 0 (0): Counter clear disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 1 (1): Counter clear enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 |
| CSCBRAH | GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Clear Enable 0 (0): Counter clear disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 1 (1): Counter clear enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 |
| CSCBFAL | GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Clear Enable 0 (0): Counter clear disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 1 (1): Counter clear enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 |
| CSCBFAH | GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Clear Enable 0 (0): Counter clear disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 1 (1): Counter clear enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 |
| CSELCA | ELC_GPTA Event Source Counter Clear Enable 0 (0): Counter clear disabled at the ELC_GPTA input 1 (1): Counter clear enabled at the ELC_GPTA input |
| CSELCB | ELC_GPTB Event Source Counter Clear Enable 0 (0): Counter clear disabled at the ELC_GPTB input 1 (1): Counter clear enabled at the ELC_GPTB input |
| CSELCC | ELC_GPTC Event Source Counter Clear Enable 0 (0): Counter clear disabled at the ELC_GPTC input 1 (1): Counter clear enabled at the ELC_GPTC input |
| CSELCD | ELC_GPTD Event Source Counter Clear Enable 0 (0): Counter clear disabled at the ELC_GPTD input 1 (1): Counter clear enabled at the ELC_GPTD input |
| CCLR | Software Source Counter Clear Enable 0 (0): Counter clear disabled by the GTCLR register 1 (1): Counter clear enabled by the GTCLR register |